Integrated circuits are typically formed on a semiconductor substrate such as a silicon wafer or other semiconducting material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. By way of example, the various materials are doped, ion implanted, deposited, etched, grown, etc. using various processes. A continuing goal in semiconductor processing is to continue to strive to reduce the size of individual electronic components thereby enabling smaller and denser integrated circuitry.
One technique for patterning and processing semiconductor substrates is photolithography. Such includes deposition of a patternable masking layer commonly known as photoresist. Such materials can be processed to modify their solubility in certain solvents, and are thereby readily usable to form patterns on a substrate. For example, portions of a photoresist layer can be exposed to actinic energy through openings in a radiation-patterning tool, such as a mask or reticle, to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed regions can be removed, depending on the type of photoresist, thereby leaving a masking pattern of the photoresist on the substrate. Adjacent areas of the underlying substrate next to the masked portions can be processed, for example by etching or ion implanting, to effect the desired processing of the substrate adjacent the masking material. In certain instances, multiple different layers of photoresist and/or a combination of photoresists with non-radiation sensitive masking materials are utilized.
The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to form patterned features, such as conductive lines. A concept commonly referred to as “pitch” can be used to describe the sizes of the features in conjunction with spaces immediately adjacent thereto. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern in a straight line cross section, thereby including the maximum width of the feature and the space to the next immediately adjacent feature. However, due to factors such as optics and light or radiation wave length, photolithography techniques tend to have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction using photolithography.
Pitch doubling or pitch multiplication is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. Such typically forms features narrower than minimum photolithography resolution by depositing spacer-forming layers to have a lateral thickness which is less than that of the minimum capable photolithographic feature size. The spacer-forming layers are commonly anisotropically etched to form sub-lithographic features, and then the features which were formed at the minimum photolithographic feature size are etched from the substrate. Using such technique where pitch is actually halved, such reduction in pitch is conventionally referred to as pitch “doubling”. More generally, “pitch multiplication” encompasses increase in pitch of two or more times and also of fractional values other than integers. Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor.
Conductive lines may be used in integrated circuitry as electrical interconnects and as bit lines in memory circuitry. Metals, whether elemental metals, alloys of different elemental metals, or conductive metal compounds, are dominant interconnect material due to their high electrical conductivity. One manner of forming conductive lines uses what is referred to as damascene processing. In such, a suitable molding material is formed over a substrate over which the conductive lines are to be formed. Trenches are etched into the molding material into desired shapes and orientations of the conductive lines being formed. The trenches are at least partially filled with conductive material in forming conductive lines within the trenches.
It is difficult to fill very narrow trenches in damascene formation of conductive lines, particularly as the width of such lines has fallen to 20 nanometers and below using pitch multiplication techniques because of resistivity requirements. Effective resistivity of the trench fill material increases at these dimensions. Additionally, voids may form within the conductive material within the trenches due to the material not spanning completely across the trench width. Voids inherently reduce the volume of conductive material in the line. Such has not been particularly problematic at trench/line widths of at least 60 nanometers.
While the invention was motivated in addressing the above-identified issues, the invention is no way so limited.